To improve the performance of an integrated circuit (“IC”), a designer must pay particular attention to factors such as the propagation delay time of critical signals propagated on particular paths. Signal propagation delay is a significant factor in high performance IC design. This is primarily due to the resistive and capacitive components of the metal interconnects (also known in the art as “buses,” “bus lines,” “nets,” or “wires”) between circuit elements of the IC. In general, signal propagation delay increases as a function of bus length. Signal propagation delay not only slows performance of an IC, but also if the signal propagation delay exceeds the period of an IC clock, the IC will not function properly.
Similarly, signal transition time is another significant factor in high performance IC design. The resistive and capacitive components of the buses also affect transition time of the signals being propagated. A transition time that is too long permits noise to couple to the signal, which can cause unexpected transitions of the signal. Additionally, a long transition time may worsen the propagation delay of a signal. As a result, too long of a signal transition time may cause functional errors or failures.
IC designers address the issue of signal propagation delay and signal transition time using repeaters. Inserting one or more repeater amplifiers (i.e., “repeaters”), also known as drivers or buffers, into a long bus path can decrease the resistive-capacitive delay and degradation of the propagated signal. A repeater is generally a circuit such as, for example, an inverter or a set of cascaded inverters. Thus, where a critical bus is relatively long, the signal propagation delay associated with that critical bus can be decreased by rerouting the path to include a repeater.
Conventionally, repeater placement in an IC has been an iterative process, evaluated by a designer. While software tools for modeling and simulating circuits exist, they do not automatically determine where, and to what extent, repeaters should be placed within a circuit.
Because critical paths are typically identified while designing buses for an IC, critical paths are usually not determined until after the block-level architectures are completed. If signals are routed in the entire chip using available metal layers including lower metal layers, repeater resources may be exhausted quickly without resolving IC timing. On the other hand, if signals are virtually routed to converge on timing for the entire chip, they may be physically unroutable. Further, continuously shrinking die sizes and increasing numbers of gates used in System-On-Chip (SOC) microprocessors have shrunk the floor plan channels. Accordingly, designers seek to place only as many repeaters as necessary on an integrated circuit to avoid timing malfunctions, while avoiding the consumption of too much space on the IC.